1. Field of the Invention
The present invention relates generally to integrated circuit technology and, more specifically, the present invention relates to the testing of integrated circuits.
2. Description of the Related Art
To achieve high performances in modem integrated circuits, it is often necessary to utilize high speed communications busses. As integrated circuit technologies continue to advance, the frequencies at which the integrated circuits operate increase accordingly. It has been a considerable challenge for circuit designers to design busses that are able to match the speed performance of the core speed of modern central processing units (CPUs). One reason for the difficulty of continuously increasing bus speeds to match the continuously increasing CPU core speeds is that input/output buffers coupled to the busses must often operate across a wide variety of operating conditions. For instance, the performance of an input/output buffer changes with respect to conditions such as process, voltage and temperature.
The use of impedance compensated input/output buffers have provided one prior art solution to the problems associated with the changes in operating conditions such as process, voltage and temperature. Impedance compensated input/output buffers address the problems associated with varying conditions by providing mechanisms to help maintain the optimum characteristics of input/output buffer drivers over a wide range of operating conditions.
FIG. 1 is an illustration of a prior art impedance compensated input/output buffer 101 that employs digital impedance compensation, which relies basically on the same principles as an analog-to-digital converter. In this scheme, output buffers and their pre-drivers include a plurality of transistors 107A-C coupled in parallel between an output pin 113 and ground. Compensation unit 121 generates digital information via signals 111A-C, which indicate the number of parallel coupled transistors 107A-C in every buffer that should be activated at any given time to compensate for varying operating conditions. For example, under slow operating conditions, which include low voltage, high temperature and slow process corner, many transistors 107A-C may need to be activated to pull the voltage at output pin 113 to ground. In contrast, under faster operating conditions, fewer parallel coupled transistors 107A-C may need to be switched on for similar performance.
Although prior art input/output buffer 101 has the ability to compensate for varying operating conditions, one problem with input/output buffer 101 is that it is difficult to test the functionality of each of the devices since the parallel coupled transistors create logic redundancies. For instance, transistors 107A-C as well as transistors 109A-C are coupled in parallel between output pin 113 and ground and node 119 and ground respectively. For optimum performance, it is desired that all transistors 107A-C and 109A-C are completely functional.
It is possible in a testing environment, that due to a defect, one or more of the parallel coupled devices 107A-C and 109A-C may not function properly, but the remaining devices could still function properly and a tester (not shown) coupled to output pin 113 and node 119 would be unable to detect a defective device based on logic levels or simple timing. As a consequence, that defective device may not be detected in a testing environment but could, however, cause input/output buffer 101 to fail in a system environment.
Therefore, what is desired is a method and an apparatus for testing the parallel coupled devices in compensated input/output buffers that are otherwise not testable due to the logic redundancies created by the parallel coupled nature of the devices in compensated input/output buffers. Such a method and apparatus would verify functionality of all compensation devices in compensated input/buffers. Moreover, in a built-in self-test implementation, such a method and an apparatus would eliminate the need for any additional test equipment.